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-- Company: 
-- Engineer: 
-- 
-- Create Date: 23.04.2024 17:53:51
-- Design Name: 
-- Module Name: majority - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Majority_LUT is
    Port (
        x : in STD_LOGIC_VECTOR (2 downto 0);      
        out1 : out STD_LOGIC
    );
end Majority_LUT;

architecture Behavioral of Majority_LUT is
begin
    process(x)
    begin
        case (x) is
            when "000" => out1 <= '0';
            when "001" => out1 <= '0';
            when "010" => out1 <= '0';
            when "011" => out1 <= '1';
            when "100" => out1 <= '0';
            when "101" => out1 <= '1';
            when "110" => out1 <= '1';
            when "111" => out1 <= '1';
            when others => out1 <= '0'; -- Covers any unexpected cases
        end case;
    end process;
end Behavioral;